Field of the Invention
Embodiments of the disclosure generally relate to methods and a system for substrate strain variation reduction, more specifically, methods and a system for substrate strain variation reduction for lithography process on a semiconductor substrate using laser energy treatment process.
Description of the Related Art
In the manufacture of integrated circuits (IC), or chips, patterns representing different layers of the chip are created by a chip designer. A series of reusable masks, or photomasks, are created from these patterns in order to transfer the design of each chip layer onto a semiconductor substrate during the manufacturing process. Mask pattern generation systems use precision lasers or electron beams to image the design of each layer of the chip onto a respective mask. The masks are then used much like photographic negatives to transfer the circuit patterns for each layer onto a semiconductor substrate. These layers are built up using a sequence of processes and translate into the tiny transistors and electrical circuits that comprise each completed chip. Typically, devices on semiconductor substrates are manufactured by a sequence of lithographic processing steps in which the devices are formed from a plurality of overlying layers, each having an individual pattern. Generally, a set of 15 to 100 masks is used to construct a chip and can be used repeatedly.
Between one layer and the next layer that overlays the previous one, the individual patterns of the one layer and the next layer must be aligned. A measurement of alignment marks may be obtained by a metrology tool which is then used by a lithography tool to align the subsequent layers during exposure and again after a lithography process to recheck a performance of the alignment. However, film stress/strain variations (or pattern registration errors) between layers are inevitable, and error budgets are calculated by IC designers for which the manufacturing must meet. Film stress/strain variations of the device structure may originate from different error sources, such as film stress/strain variations from previous exposure tool/metrology tool, current exposure tool/metrology tool, a matching error between the film stress/strain variations of the previous exposure tool/metrology tool and of the current exposure tool/metrology tool, or substrate film layer deformation caused by film stress and the like.
FIG. 1 depicts an overlay error map 100 of a semiconductor substrate measured after a sequence of lithographic exposure processes. In the embodiment of FIG. 1, some patterns shown in an enlarged portion 102 of the substrate are shifted or displaced from their designed location. As discussed above, displacement or misalignment of the patterns creates film stress/strain variations that may be detriment to device performance.
FIG. 2 depict another schematic view of device dies 202, 204, 206 formed on a substrate 200. The dies 202, 2041, 206 are typically designed to have a substantially square-like outline if substantially no film stress/strain variations or pattern displacement has occurred during fabrication. However, when film stress/strain variations, film stress/strain variations or pattern displacement undesirably occurs, the size, dimension or structures of dies 202, 204, 206 formed on the substrate 200 may be irregularly deformed or distorted, thus increasing likelihood of misalignment between the film layers stacked thereon that may adversely increase the probability of misalignment in the subsequent lithographic exposure process.
With the shrink of critical dimensions (CD), film stress/strain variations in the critical layers of the device structure must be minimal or eliminated in order to reliably produce devices with minimal feature sizes, such as a width of a control gate in a device. To eliminate the likelihood of film stress/strain variations, a single exposure lithographic tool is used in many cases to pattern successive layers in an attempt to eliminate tool to tool imprecision errors. However, this approach often creates logistic problems and adversely increases manufacture cycle time. Furthermore, overlay specifications have become more challenging that the non-lithographic contributions (i.e., film stress) to film stress/strain variations through stress induced substrate distortion, may alone exceed the error budget.
Therefore, there exists a need for improved methods and system to correct film stress/strain variations prior to performing lithographic exposure processes so as to improve device performance and maintain predicable product reliability and yield.